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1/57 preliminary data february 2003 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. M30LW128D 128 mbit (two 64mbit, x8/x16, uniform block, flash memories) 3v supply, multiple memory product features summary n two m58lw064d 64mbit flash memories stacked in a single package n wide x8 or x16 data bus for high bandwidth n supply voltage Cv dd = 2.7 to 3.6v for program, erase and read operations Cv ddq = 1.8 to v dd for i/o buffers n access time C random read 110ns C page mode read 110/25ns n programming time C 16 word write buffer C 16s word effective programming time n 128 uniform 64 kword/128kbyte memory blocks n block protection/ unprotection n program and erase su spend n 128 bit protection register n common flash interface n 100, 000 program/er ase cycles per block n electronic signature C manufacturer code: 20h C device code M30LW128D: 8817h figure 1. packages tsop56 (n) 14 x 20 mm tbga64 (za) 10 x 13mm tbga fbga lfbga88 (ze) 8 x 10mm
M30LW128D 2/57 table of contents summary description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. tsop56 connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 4. tbga64 connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 5. lfbga connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 address input (a0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 address inputs (a1-a22). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 address input (a23). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 data inputs/outputs (dq0-dq15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 chip enable (e). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 output enable (g). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 write enable (w). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 reset/power-down (rp). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 byte/word organization select (byte). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 status/(ready/busy) (sts) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 program/erase enable (v pen ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 v dd supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 v ddq supply voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 v ss ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 v ssq ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 memory enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 2. single m58lw064d device enable, e2, e1 and e0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 3. M30LW128D device enable, a23 and e. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 6. stacked flash memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 7. block addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 bus operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 bus read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 bus read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 page read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 bus write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 output disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 automatic low power.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 4. bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 read memory array command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 read electronic signature command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7
3/57 M30LW128D read query command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 read status register command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 clear status register command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 block erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 word/byte program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 write to buffer and program command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 program/erase suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 program/erase resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 block protect command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 blocks unprotect command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 protection register program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 configure sts command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 5. commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 6. configuration codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 7. read electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 8. protection register memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 8. word-wide read protection register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 9. byte-wide read protection register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 10. program/erase times and program/erase endurance cycles . . . . . . . . . . . . . . . . . . . 24 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 program/erase controller status (bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 erase suspend status (bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 erase status (bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 program status (bit 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 vpen status (bit 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 program suspend status (bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 block protection status (bit 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 reserved (bit 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 11. status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 12. absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 13. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 9. ac measurement input output waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 10. ac measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 14. capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 15. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 11. bus read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1 table 16. bus read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 12. page read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 17. page read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 figure 13. write ac waveform, write enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 18. write ac characteristics, write enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
M30LW128D 4/57 figure 14. write ac waveforms, chip enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 19. write ac characteristics, chip enable controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 15. reset, power-down and power-up ac waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 20. reset, power-down and power-up ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . 35 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 16. tsop56 - 56 lead plastic thin small outline, 14 x 20 mm, package outline . . . . . . . 36 table 21. tsop56 - 56 lead plastic thin small outline, 14 x 20 mm, package mechanical data 36 figure 17. tbga64 - 10x13mm, 8 x 8 ball array 1mm pitch, package outline . . . . . . . . . . . . . . . 37 table 22. tbga64 - 10x13mm, 8 x 8 ball array, 1 mm pitch, package mechanical data . . . . . . . 37 figure 18. lfbga88 8x10 mm - 8x10 ball array, 0.8mm pitch, bottom view package outline 38 table 23. lfbga88 8x10mm - 8x10 ball array, 0.8mm pitch, package mechanical data . . . . . . 38 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 24. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 9 appendix a. block address table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 25. block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 appendix b. common flash interface - cfi. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 26. query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 27. cfi - query address and data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 28. cfi - device voltage and timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 29. device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 30. block status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 31. extended query information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 appendix c. flow charts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 19. write to buffer and program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . 46 figure 20. program suspend & resume flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . 47 figure 21. erase flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 22. erase suspend & resume flowchart and pseudo code. . . . . . . . . . . . . . . . . . . . . . . 49 figure 23. block protect flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 24. blocks unprotect flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 25. protection register program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . 52 figure 26. command interface and program erase controller flowchart (a) . . . . . . . . . . . . . . . . 53 figure 27. command interface and program erase controller flowchart (b) . . . . . . . . . . . . . . . . 54 figure 28. command interface and program erase controller flowchart (c). . . . . . . . . . . . . . . . 55 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 32. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
5/57 M30LW128D summary description the M30LW128D is a 128 mbit device that is com- posed of two separate 64 mbit m58lw064d flash memories. the device can be erased electrically at block level and programmed in-system using a 2.7v to 3.6v (v dd ) supply for the circuitry and a 1.8v to v dd (v ddq ) supply for the input/output pins. the bus width can be configured for x8 or x16 for the devices available in the tsop56 (14 x 20 mm) and tbga64 (10x13mm , 1mm pitch) packages. the bus width is set to x16 for the devices avail- able in the lfbga88 (8x10mm, 0.8mm pitch) package. each internal m58lw064d has 3 chip enable sig- nals to allow up to 4 memories to be connected to- gether without the use of additional glue logic. in this way the address space is contiguous and the microprocessor only requires one chip enable, e , to control both memories. the device is divided into 128 blocks of 1mbit (2 x 64 x 1mb) that can be erased independently so it is possible to preserve valid data while old data is erased. program and erase commands are written to the command interface of the device. an on- chip program/erase controller (p/e.c) simplifies the process of programming or erasing the device by taking care of all of the special operations that are required to update the memory contents. the end of a program or erase operation can be de- tected and any error conditions identified in the status register. the command set required to control the device is consistent with jedec stan- dards. the write buffer allows the microprocessor to pro- gram from 1 to 16 words in parallel, both speeding up the programming and freeing up the micropro- cessor to perform other work. a word program command is available to program a single word. erase can be suspended in order to perform either read or program in any other block and then re- sumed. program can be suspended to read data in any other block and then resumed. each block can be programmed and erased over 100,000 cy- cles. individual block protection against program or erase is provided for data security. all blocks are protected during power-up. the protection of the blocks is non-volatile; after power-up the protec- tion status of each block is restored to the state when power was last removed. software com- mands are provided to allow protection of some or all of the blocks and to cancel all block protection bits simultaneously. all program or erase opera- tions are blocked when the program erase enable input v pen is low. the reset/power-down pin is used to apply a hardware reset to the enabled memory and to set the device in power-down mode. the sts signal is an open drain output that can be used to identify the program/erase controller sta- tus. it can be configured in two modes: ready/ busy mode where a static signal indicates the sta- tus of the p/e.c, and status mode where a pulsing signal indicates the end of a program or block erase operation. in both modes it can be used as a system interrupt signal, useful for saving cpu time. the sts signal is only available with the tsop56 and tbga64 packages. each memory includes a 128 bit protection regis- ter. the protection register is divided into two 64 bit segments, the first one is written by the manu- facturer (contact stmicroelectronics to define the code to be written here), while the second one is programmable by the user. the user programma- ble segment can be locked.
M30LW128D 6/57 figure 2. logic diagram note: 1. not available with lfbga88 package. table 1. signal names note: 1. not available with lfbga88 package. ai07504 24 a0 (1) -a23 w dq0-dq15 v dd M30LW128D e v ss 16 g rp v ddq v pen v ssq sts (1) byte (1) a0 (1) address input (used in x8 mode only) a1-a22 address inputs a23 address input to select memory byte (1) byte/word organization select dq0-dq15 data inputs/outputs e chip enable g output enable rp reset/power-down sts (1) status/(ready/busy) v pen program/erase enable w write enable v dd supply voltage v ddq input/output supply voltage v ss ground v ssq input/output ground nc not connected internally du do not use
7/57 M30LW128D figure 3. tsop56 connections note: pin 2 (e1 for a single m58lw064d device) and pin 29 (e2 for a single m58lw064d device) are nc (not connected). they should be tied to ground (v ss ) to assure compatibility with a single chip 128mbit device. dq3 dq9 dq2 dq0 dq6 a16 a17 a18 dq14 dq12 dq10 sts v ddq dq4 dq7 ai07508 M30LW128D 14 1 15 28 29 42 43 56 dq8 v dd dq1 dq11 a0 a20 a21 nc a19 w nc e nc byte a6 a3 a8 a9 a10 a2 a7 v pen a1 a4 a5 a12 a13 a11 a15 a14 rp v ss dq13 dq15 v dd dq5 g v ss v ssq a22 a23
M30LW128D 8/57 figure 4. tbga64 connections (top view through package) note: ball b8 (e1 for a single m58lw064d device) and ball h1(e2 for a single m58lw064d device) are nc (not connected). they shou ld be tied to ground (v ss ) to assure compatibility with a single chip 128mbit device. ai07505 dq6 a1 v ssq v dd dq10 v dd dq7 dq5 v ddq dq2 h dq14 v ss dq13 d a16 a20 e a9 c a17 a21 a11 a15 byte a8 b a19 a2 a13 a14 a 8 7 6 5 4 3 2 1 a7 a3 a4 a5 g f e dq0 a6 v pen a18 a10 a12 rp dq15 sts dq9 dq8 dq1 dq4 dq3 g dq12 dq11 w v ss du du du du du du du du nc a22 nc a23 nc a0
9/57 M30LW128D figure 5. lfbga connections (top view through package) note: 1. the byte , sts and a0 connections are not available with the lfbga88 package. 8 7 6 5 4 3 2 1 c b a21 a4 a11 d e f du du w a19 a18 a22 a5 a12 v ss nc nc a9 a3 a13 v pen nc a17 a10 a20 a2 a15 nc a7 a14 a8 a1 a16 rp nc a6 dq13 a0 dq5 dq10 dq2 dq8 dq7 dq14 nc dq12 dq3 dq1 dq0 dq15 dq6 dq4 dq11 dq9 g v ddq e nc nc v ss v ssq v dd nc v ddq v ssq du du du du du du a g h j k ai07555 l m nc nc nc du nc nc nc v ddq nc nc nc v dd nc nc nc nc nc nc v dd nc
M30LW128D 10/57 signal descriptions see figure 2, logic diagram and table 1, signal names, for a brief overview of the signals connect- ed to this device. address input (a0). the a0 address input is used to select the higher or lower byte in x8 mode. it is not used in x16 mode (where a1 is the lowest significant bit). the a0 address input is not available with the lfbga88 package. address inputs (a1-a22). the address inputs are used to select the cells to access in the mem- ory array during bus read operations either to read or to program data to. during bus write oper- ations they control the commands sent to the command interface of the internal state machine. the device must be enabled (refer to table 3, M30LW128D device enable) when selecting the addresses. the address inputs are latched on the rising edge of write enable or chip enable, e , whichever occurs first. address input (a23). address input a23 is used to select between the two internal memories. when it is high, v ih , it selects the upper memory, when it is low, v il , it selects the lower memory. refer to memory enable section for more details. data inputs/outputs (dq0-dq15). the data in- puts/outputs output the data stored at the selected address during a bus read operation, or are used to input the data during a program operation. dur- ing bus write operations they represent the com- mands sent to the command interface of the internal state machine. when used to input data or write commands they are latched on the rising edge of write enable or chip enable, e , whichever occurs first. when the device is enabled and output enable is low, v il , the data bus outputs data from the mem- ory array, the electronic signature, the block pro- tection status, the cfi information or the contents of the status register. the data bus is high imped- ance when the device is deselected, output en- able is high, v ih, or the reset/power-down signal is low, v il . when the program/erase controller is active the ready/busy status is given on dq7. chip enable (e ). the chip enable input acti- vates the memory control logic, input buffers, de- coders and sense amplifiers. the M30LW128D stacked memory uses the a23 address line and the external chip enable, e , to select and enable the internal memories. refer to memory enable section and table 3, for more details. when the chip enable deselects the memory, power consumption is reduced to the standby lev- el, i dd1 . output enable (g ). the output enable, g , gates the outputs through the data output buffers during a read operation. when output enable, g , is at v ih the outputs are high impedance. write enable (w ). the write enable input, w , controls writing to the command interface, input address and data latches. both addresses and data can be latched on the rising edge of write en- able. reset/power-down (rp ). the reset/power- down signal can be used to apply a hardware re- set to the memory. a hardware reset is achieved by holding reset/ power-down low, v il , for at least t plph . when reset/power-down is low, v il , the status regis- ter information is cleared and the power consump- tion is reduced to power-down level. the device is deselected and outputs are high impedance. if re- set/power-down goes low, v il ,during a block erase, a write to buffer and program or a block protect/unprotect the operation is aborted and the data may be corrupted. in this case the sts pin stays low, v il , for a maximum timing of t plph + t ph- bh, until the completion of the reset/power-down pulse. after reset/power-down goes high, v ih , the de- vice will be ready for bus read and bus write op- erations after t phqv . note that sts does not fall during a reset, see ready/busy output section. in an application, it is recommended to associate reset/power-down pin, rp , with the reset signal of the microprocessor. otherwise, if a reset opera- tion occurs while the device is performing an erase or program operation, the device may out- put the status register information instead of be- ing initialized to the default asynchronous random read. byte/word organization select (byte ). the byte/word organization select signal is used to switch between the x8 and x16 bus widths of the memory. when byte/word organization select is low, v il , the memory is in x8 mode, when it is high, v ih , the memory is in x16 mode. the byte/word organization select signal is not available with the lfbga88 package. status/(ready/busy) (sts). the sts signal is an open drain output that can be used to identify the program/erase controller status. it can be configured in two modes: n ready/busy - the pin is low, v ol , during program and erase operations and high impedance when the memory is ready for any read, program or erase operation.
11/57 M30LW128D n status - the pin gives a pulsing signal to indicate the end of a program or block erase operation. after power-up or reset the sts pin is configured in ready/busy mode. the pin can be configured for status mode using the configure sts com- mand. when the program/erase controller is idle, or sus- pended, sts can float high through a pull-up re- sistor. the use of an open-drain output allows the sts pins from several devices to be connected to a single pull-up resistor (a low will indicate that one, or more, of the memories is busy). sts is not low during a reset unless the reset was applied when the program/erase controller was active. the sts signal is not available with the lfbga88 package. program/erase enable (v pen ). the program/ erase enable input, v pen, is used to protect all blocks, preventing program and erase operations from affecting their data. program/erase enable must be kept high during all program/erase controller operations, other- wise the operations is not guaranteed to succeed and data may become corrupt. v dd supply voltage. v dd provides the power supply to the internal core of the device. it is the main power supply for all operations (read, pro- gram and erase). v ddq supply voltage. v ddq provides the power supply to the i/o pins and enables all outputs to be powered independently from v dd . v ddq can be tied to v dd or can use a separate supply. it is recommended to power-up and power-down v dd and v ddq together to avoid any condition that would result in data corruption. v ss ground. ground, v ss, is the reference for the core power supply. it must be connected to the system ground. v ssq ground. v ssq ground is the reference for the input/output circuitry driven by v ddq . v ssq must be connected to v ss . note: each device in a system should have v dd and v ddq decoupled with a 0.1f ceramic capacitor close to the pin (high frequency, in- herently low inductance capacitors should be as close as possible to the package). see fig- ure 10, ac measurement load circuit.
M30LW128D 12/57 memory enable each internal m58lw064d memory has 3 chip enable signals to allow up to 4 memories to be connected together without the use of additional glue logic, see table 2, single m58lw064d de- vice enable. in this way the address space is con- tiguous and the microcontroller only requires one chip enable, e , to control both memories. figure 6 shows how a 128mbit stacked flash memory is created using two m58lw064d memo- ries. one of the memories is located in the upper address space and is referred to as the upper memory, the other is located in the lower address space and is referred to as the lower memory, see figure 7, block addresses. the e0, e1 and e2 chip enables of each m58lw064d memory are connected internally, as shown in figure 6. the external signal a23 is used to select between the upper and lower memories. a23 is connected to e2 of the upper memory and to e1 of the lower memory. e1 of the upper memory is always connected to v dd while e2 of the lower memory is always con- nected to v ss . the external chip enable, e , is used to enable or disable the memory selected by a23, see table 3, M30LW128D device enable. e is connected to the e0 signal of both memories. the M30LW128D (tsop56 and tbga64 packag- es only) supports both x8 and x16 bus widths. it is also possible to have a x32 bus width by connect- ing two x16 bus width M30LW128D devices to- gether. note that the two M30LW128D devices must use the same e0 as chip enable, as e1 and e2 are not connected internally. table 2. single m58lw064d device enable, e2, e1 and e0 table 3. M30LW128D device enable, a23 and e note: 1. um = upper memory, lm = lower memory. e2 e1 e0 device v il v il v il enabled v il v il v ih disabled v il v ih v il disabled v il v ih v ih disabled v ih v il v il enabled v ih v il v ih enabled v ih v ih v il enabled v ih v ih v ih disabled a23 internal signals chip enable, e upper memory lower memory e2 um = e1 lm (1) e1 um (1) e2 lm (1) e0 um = e0 lm (1) v il v dd (v ih )v ss (v il ) v il disabled enabled v il v ih disabled disabled v ih v il enabled disabled v ih v ih disabled disabled
13/57 M30LW128D figure 6. stacked flash memory ai07506 dq0-dq15 a0-a22 64 mbit lower memory 64 mbit upper memory e1 e1 e0 e0 e2 e2 e a23 v dd package v ss
M30LW128D 14/57 figure 7. block addresses note: also see appendix a, table 25 for a full listing of the block addresses ai07507 1 mbit or 128 kbytes 3fffffh 3f0000h 1 mbit or 128 kbytes 01ffffh 010000h 1 mbit or 128 kbytes 00ffffh 000000h 1 mbit or 128 kbytes 3effffh 3e0000h lower memory total of 64 1 mbit blocks 7fffffh 7e0000h 03ffffh 020000h 01ffffh 000000h 7dffffh 7c0000h 1 mbit or 64 kwords 1 mbit or 64 kwords 1 mbit or 64 kwords 1 mbit or 64 kwords 1 mbit or 128 kbytes 7fffffh 7f0000h 1 mbit or 128 kbytes 41ffffh 410000h 1 mbit or 128 kbytes 40ffffh 400000h byte (x8) bus width word (x16) bus width 1 mbit or 128 kbytes 7effffh 7e0000h upper memory total of 64 1 mbit blocks ffffffh fe0000h 83ffffh 820000h 81ffffh 800000h fdffffh fc0000h 1 mbit or 64 kwords 1 mbit or 64 kwords 1 mbit or 64 kwords 1 mbit or 64 kwords
15/57 M30LW128D bus operations there are 6 bus operations that control each mem- ory. each of these is described in this section, see tables 4, bus operations, for a summary. on power-up or after a hardware reset the device defaults to read array mode (page read). typically glitches of less than 5ns on chip enable or write enable are ignored by the device and do not affect bus operations. bus read. bus read operations read from the memory cells, or specific registers (electronic sig- nature, status register, cfi and block protection status) in the command interface. a valid bus operation involves setting the desired address on the address inputs, enabling the de- vice (refer to table 3), applying a low signal, v il , to output enable and keeping write enable high, v ih . the data inputs/outputs will output the value, see figure 11, bus read ac waveforms, and table 16, bus read ac characteristics, for details of when the output becomes valid. page read. page read operations are used to read from several addresses within the same memory page. each memory page is a 4 words or 8 bytes and has the same a3-a22. in x8 mode only a0, a1 and a2 may change, in x16 mode only a1 and a2 may change. valid bus operations are the same as bus read operations but with different timings. the first read operation within the page has identical timings, subsequent reads within the same page have much shorter access times. if the page changes then the normal, longer timings apply again. see figure 12, page read ac waveforms and table 17, page read ac characteristics for details on when the outputs become valid. bus write. bus write operations write to the command interface in order to send commands to the device or to latch addresses and input data to program. a valid asynchronous bus write operation begins by setting the desired address on the address in- puts and enabling the device (refer to chip enable section). both the address inputs and data input/outputs are latched by the command interface on the ris- ing edge of write enable or chip enable, whichev- er occurs first. output enable must remain high, v ih , during the whole bus write operation. see figures 13, and 14, write ac waveforms, and tables 18 and 19, write and chip enable controlled write ac char- acteristics, for details of the timing requirements. output disable. the data inputs/outputs are in the high impedance state when the output enable is high. standby. when chip enable is high, v ih , the de- vice enters standby mode and the data inputs/ outputs pins are placed in the high impedance state regardless of output enable or write enable. the supply current is reduced to the standby supply current, i dd1 . during program or erase operations the device will continue to use the program/erase supply current, i dd3 , for program or erase operations un- til the operation completes. automatic low power. if there is no change in the state of the bus for a short period of time during asynchronous bus read operations the device enters auto low power mode where the internal supply current is reduced to the auto-standby supply current, i dd5 . the data inputs/outputs will still output data if a bus read operation is in progress. automatic low power is only available in asyn- chronous read modes. power-down. the device is in power-down mode when reset/power-down, rp , is low. the power consumption is reduced to the power-down level, i dd2 , and the outputs are high impedance, independent of chip enable, output enable or write enable.
M30LW128D 16/57 table 4. bus operations note: 1. dq8-dq15 are high z in x8 mode. 2. x = dont care v il or v ih . high = v ih or v hh . bus operation memory enabled a23 e g w rp a1-a22 (x16) a0-a22 (x8) dq0-dq15 (x16) dq0-dq7 (x8) (1) bus read upper v ih v il v il v ih high address data output lower v il page read upper v ih v il v il v ih high address data output lower v il bus write upper v ih v il v ih v il high address data input lower v il output disable output disabled x v il v ih v ih high x high z standby device disabled x v ih x x high x high z power-down device disabled x x xx v il x high z
17/57 M30LW128D command interface all bus write operations to the device are inter- preted by the command interface. commands consist of one or more sequential bus write oper- ations. as the device contains two internal memo- ries care must be taken to issue the commands to the correct address. commands issued with a23 high will be addressed to the upper memory, com- mands issued with a23 low will be addressed to the lower memory. the commands are summarized in table 5, com- mands. refer to table 5 in conjunction with the text descriptions below. after power-up or a reset operation the device en- ters read mode. read memory array command. the read mem- ory array command is used to return the device to read mode. one bus write cycle is required to is- sue the read memory array command and return the device to read mode. once the command is issued the device remains in read mode until an- other command is issued. from read mode bus read operations will access the memory arrays. after power-up or a reset the device defaults to read array mode (page read). while the program/erase controller is executing a program, erase, block protect, blocks unprotect or protection register program operation the de- vice will not accept the read memory array com- mand until the operation completes. read electronic signature command. the read electronic signature command is used to read the manufacturer code, the device code, the block protection status and the protection register. one bus write cycle is required to issue the read electronic signature command. once the com- mand is issued subsequent bus read operations read the manufacturer code, the device code, the block protection status or the protection register until another command is issued. refer to table 7, read electronic signature, tables 8 and 9, word and byte-wide read protection register and fig- ure 8, protection register memory map for infor- mation on the addresses. read query command. the read query com- mand is used to read data from the common flash interface (cfi) memory area. one bus write cycle is required to issue the read query command. once the command is issued subsequent bus read operations read from the common flash in- terface memory area. see appendix b, tables 26, 27, 28, 29, 30 and 31 for details on the information contained in the common flash interface (cfi) memory area. read status register command. the read sta- tus register command is used to read the status register. one bus write cycle is required to issue the read status register command. as the device contains two status registers (one for each inter- nal memory) the command must be issued to the same address as the previous operation (block erase, write to buffer, word program etc.). once the command is issued subsequent bus read op- erations to the same internal memory (a23 low or a23 high depending on where the command was issued to) read the status register until another command is issued. if the bus read operation is issued to the other internal memory, then the other status register will be read, giving the status of the last command issued in the other internal memory. the status register information is present on the output data bus (dq1-dq7) when the device is en- abled and output enable is low, v il . see the section on the status register and table 11 for details on the definitions of the status reg- ister bits clear status register command. the clear sta- tus register command can be used to reset bits 1, 3, 4 and 5 in the status register to 0. one bus write is required to issue the clear status register command. the command must be issued to the same address as the previous operation (block erase, write to buffer, word program etc.). the bits in the status register are sticky and do not automatically return to 0 when a new write to buffer and program, erase, block protect, block unprotect or protection register program com- mand is issued. if any error occurs then it is essen- tial to clear any error bits in the status register by issuing the clear status register command before attempting a new program, erase or resume command. block erase command. the block erase com- mand can be used to erase a block. it sets all of the bits in the block to 1. all previous data in the block is lost. if the block is protected then the erase operation will abort, the data in the block will not be changed and the status register will output the error. two bus write operations are required to issue the command; the second bus write cycle latches the block address in the internal state machine and starts the program/erase controller. once the command is issued subsequent bus read opera- tions read the status register. see the section on the status register for details on the definitions of the status register bits. during erase, the device being erased will only ac- cept the read status register and program/erase suspend commands, ignoring all other com- mands. the device not being erased will accept
M30LW128D 18/57 any command. typical erase times are given in table 10. see appendix c, figure 21, block erase flow- chart and pseudo code, for a suggested flowchart on using the block erase command. word/byte program command. the word/ byte program command is used to program a sin- gle word or byte in the memory array. two bus write operations are required to issue the com- mand; the first write cycle sets up the word pro- gram command, the second write cycle latches the address and data to be programmed in the internal state machine and starts the program/erase con- troller. if the block being programmed is protected an er- ror will be set in the status register and the oper- ation will abort without affecting the data in the memory array. the block must be unprotected us- ing the blocks unprotect command. write to buffer and program command. the write to buffer and program command is used to program the memory array. if the command is is- sued with a23 high the upper memory will be pro- grammed, if the command is issued with a23 low the lower memory will be programmed. up to 16 words/32 bytes can be loaded into the write buffer and programmed into the memory ar- ray. each write buffer has the same a5-a22 ad- dresses. in byte-wide mode only a0-a4 may change, in word-wide mode only a1-a4 may change. four successive steps are required to issue the command. 1. one bus write operation is required to set up the write to buffer and program command. is- sue the set up command with the selected memory block address where the program op- eration should occur (any address in the block where the values will be programmed can be used). any bus read operations will start to out- put the status register after the 1st cycle. 2. use one bus write operation to write the same block address along with the value n on the data inputs/output, where n+1 is the number of words/bytes to be programmed. 3. use n+1 bus write operations to load the ad- dress and data for each word into the write buffer. the addresses must have the same a5- a22. 4. finally, use one bus write operation to issue the final cycle to confirm the command and start the program operation. invalid address combinations or failing to follow the correct sequence of bus write cycles will set an error in the status register and abort the oper- ation without affecting the data in the memory ar- ray. the status register should be cleared before re-issuing the command. if the block being programmed is protected an er- ror will be set in the status register and the oper- ation will abort without affecting the data in the memory array. the block must be unprotected us- ing the blocks unprotect command. see appendix c, figure 19, write to buffer and program flowchart and pseudo code, for a sug- gested flowchart on using the write to buffer and program command. program/erase suspend command. the pro- gram/erase suspend comm and is used to pause a write to buffer and program or erase operation. the command will only be accepted during a pro- gram or an erase operation. it can be issued at any time during an erase operation but will only be accepted during a write to buffer and program command if the program/erase controller is run- ning. one bus write cycle is required to issue the pro- gram/erase suspend command and pause the program/erase controller. the command must be issued to the same address as the current pro- gram or erase operation. once the command is is- sued it is necessary to poll the program/erase controller status bit (bit 7) to find out when the program/erase controller has paused; no other commands will be accepted until the program/ erase controller has paused. after the program/ erase controller has paused, the device will con- tinue to output the status register until another command is issued. during the polling period between issuing the pro- gram/erase suspend command and the program/ erase controller pausing, it is possible for the op- eration to complete. once the program/erase controller status bit (bit 7) indicates that the pro- gram/erase controller is no longer active, the pro- gram suspend status bit (bit 2) or the erase suspend status bit (bit 6) can be used to deter- mine if the operation has completed or is suspend- ed. for timing on the delay between issuing the program/erase suspend command and the pro- gram/erase controller pausing see table 10. during program/erase suspend the read memo- ry array, read status register, read electronic signature, read query and program/erase re- sume commands will be accepted by the com- mand interface. additionally, if the suspended operation was erase then the word program, write to buffer and program, and program sus- pend commands will also be accepted. when one of the devices is being program or erase suspended, any command issued to the other internal flash memory will be accepted. when a program operation is completed inside a
19/57 M30LW128D block erase suspend the read memory array command must be issued to reset the device in read mode, then the erase resume command can be issued to complete the whole sequence. only the blocks not being erased may be read or programmed correctly. see appendix c, figure 20, program suspend & resume flowchart and pseudo code, and figure 22, erase suspend & resume flowchart and pseudo code, for suggested flowcharts on using the program/erase suspend command. program/erase resume command. the pro- gram/erase resume command can be used to re- start the program/erase controller after a program/erase suspend operation has paused it. one bus write cycle is required to issue the pro- gram/erase resume command. the command must be issued to the same address as the pro- gram/erase suspend command. once the com- mand is issued subsequent bus read operations read the status register. block protect command. the block protect command is used to protect a block and prevent program or erase operations from changing the data in it. two bus write cycles are required to is- sue the block protect command; the second bus write cycle latches the block address in the inter- nal state machine and starts the program/erase controller. once the command is issued subse- quent bus read operations read the status reg- ister. see the section on the status register for details on the definitions of the status register bits. during the block protect operation the device will only accept the read status register command. all other commands will be ignored. typical block protection times are given in table 10. the block protection bits are non-volatile, once set they remain set through reset and power- down/power-up. they are cleared by a blocks un- protect command. see appendix c, figure 23, block protect flow- chart and pseudo code, for a suggested flowchart on using the block protect command. blocks unprotect command. the blocks un- protect command is used to unprotect all of the blocks. to unprotect all of the blocks in both of the internal memories the command must be issued to both memories, that is first with a23 low and then with a23 high. four bus write cycles are required to issue the blocks unprotect command; the first two are writ- ten with a23 low, the second two are written with a23 high. once the command is issued subse- quent bus read operations read the status reg- ister. see the section on the status register for details on the definitions of the status register bits. during the blocks unprotect operation the device will only accept the read status register com- mand. all other commands will be ignored. typical block protection times are given in table 10. see appendix c, figure 24, blocks unprotect flowchart and pseudo code, for a suggested flow- chart on using the blocks unprotect command. protection register program command. the protection register program command is used to program the 64 bit user segment of the protection register. only the lower address pro- tection register is available to the customer (a23 low), the other protection register is reserved. two write cycles are required to issue the protec- tion register program command. n the first bus cycle sets up the protection register program command. n the second latches the address and the data to be written to the protection register and starts the program/erase controller. read operations output the status register con- tent after the programming has started. the user-programmable segment can be locked by programming bit 1 of the protection register lock location to 0 (see table 8 and x for word- wide and byte-wide protection addressing). bit 0 of the protection register lock location locks the factory programmed segment and is programmed to 0 in the factory. the locking of the protection register is not reversible, once the lock bits are programmed no further changes can be made to the values stored in the protection register, see figure 8, protection register memory map. at- tempting to program a previously protected pro- tection register will result in a status register error. the protection register program cannot be sus- pended. see appendix c, figure 25, protection register program flowchart and pseudo code, for the flowchart for using the protection register program command. configure sts command. the configure sts command is used to configure the status/(ready/busy) pin. it has to be config- ured for both internal memories, that is the com- mand has to be issued first with a23 low and then with a23 high. after power-up or reset the sts pin is configured in ready/busy mode. the pin can be configured in status mode using the configure sts command (refer to status/(ready/busy) sec- tion for more details. four bus write cycles are required to issue the configure sts command. the first two cycles
M30LW128D 20/57 must be written with a23 low and the second two with a23 high. n the first bus cycle sets up the configure sts command. a23 must be low. n the second bus write cycle specifies one of the four possible configurations, a23 must be low, (refer to table 6, configuration codes): C ready/busy mode C pulse on erase complete mode C pulse on program complete mode C pulse on erase or program complete mode n the third bus write cycle re-sets up the configure sts command. this time a23 must be high. n the fourth re-specifies the configuration code given in the second bus write cycle. a23 must be high. the device will not accept the configure sts com- mand while the program/erase controller is busy or during program/erase suspend. when sts pin is pulsing it remains low for a typical time of 250ns. any invalid configuration code will set an error in the status register. the configure sts command is not available with the lfbga88 package. table 5. commands note: 1. x dont care; ra read address, rd read data, ida identifier address, idd identifier data, srd status register data, pa program address, pd program data, qa query address, qd query data, ba any address in block, pra protection register address, prd protection register data, cc configuration code. the shaded areas highlight the differences with a single m58lw064d memory. 2. for identifier addresses and data refer to table 7, read electronic signature. 3. for query address and data refer to appendix b, cfi. 4. not available with lfbga88 package. command cycles bus operations 1st cycle 2nd cycle subsequent final op. addr. data op. addr. data op. addr. data op. addr. data read memory array 2 write ra ffh read ra rd read electronic signature 3 2 write x 90h read ida (2) idd (2) read status register 2 write pa/ba 70h read pa/ba srd read query 3 2 write x 98h read qa (3) qd (3) clear status register 1 write pa/ba 50h block erase 2 write ba 20h write ba d0 word/byte program 2 write pa 40h 10h write pa pd write to buffer and program 4+n write ba e8h write ba n write pa pd write ba d0h program/erase suspend 1 write pa/ba b0h program/erase resume 1 write pa/ba d0h block protect 2 write ba 60h write ba 01h blocks unprotect 4 write 000000h 60h write 000000h d0h write 400000h 60h write 400000h d0h protection register program 2 write pra c0h write pra prd configure sts command (4) 4 write 000000h b8h write 000000h cc write 400000h b8h write 400000h cc
21/57 M30LW128D table 6. configuration codes note: 1. dq2-dq7 are reserved 2. when sts pin is pulsing it remains low for a typical time of 250ns. table 7. read electronic signature note: 1. sba is the start base address of each block, prd is protection register data. 2. base address, refer to figure 8 and tables 8 and 9 for more information. a23 must be low to address the customers protection register. the other protection register is reserved. 3. a0 is not used in read electronic signature in either x8 or x16 mode. the data is always presented on the lower byte in x16 m ode. configuration code dq1 dq2 mode sts pin description 00h 0 0 ready/busy v ol during p/e operations hi-z when the memory is ready the sts pin is low during program and erase operations and high impedance when the memory is ready for any read, program or erase operation. 01h 0 1 pulse on erase complete pulse low then high when operation completed (2) supplies a system interrupt pulse at the end of a block erase operation. 02h 1 0 pulse on program complete supplies a system interrupt pulse at the end of a program operation. 03h 1 1 pulse on erase or program complete supplies a system interrupt pulse at the end of a block erase or program operation. code bus width address (a23-a1) (3) data (dq15-dq0) manufacturer code x8 000000h 20h x16 0020h device code x8 000001h 17h x16 8817h block protection status x8 sba (1) +02h 00h (block unprotected) 01h (block protected) x16 0000h (block unprotected) 0001h (block protected) protection register x8, x16 000080h (2) prd (1)
M30LW128D 22/57 figure 8. protection register memory map table 8. word-wide read protection register word use a8a7a6a5a4a3a2a1 lock factory, user 1 0 000000 0 factory (unique id) 1 0 000001 1 factory (unique id) 1 0 000010 2 factory (unique id) 1 0 000011 3 factory (unique id) 1 0 000100 4 user 10000101 5 user 10000110 6 user 10000111 7 user 10001000 ai05501 user programmable unique device number protection register lock 1 0 88h 85h 84h 81h 80h word address
23/57 M30LW128D table 9. byte-wide read protection register word use a8a7a6a5a4a3a2a1 lock factory, user 1 0 000000 lock factory, user 1 0 000000 0 factory (unique id) 1 0 000001 1 factory (unique id) 1 0 000001 2 factory (unique id) 1 0 000010 3 factory (unique id) 1 0 000010 4 factory (unique id) 1 0 000011 5 factory (unique id) 1 0 000011 6 factory (unique id) 1 0 000100 7 factory (unique id) 1 0 000100 8 user 10000101 9 user 10000101 a user 10000110 b user 10000110 c user 10000111 d user 10000111 e user 10001000 f user 10001000
M30LW128D 24/57 table 10. program/erase times and program/erase endurance cycles note: 1. typical values measured at room temperature and nominal voltages. 2. sampled, but not 100% tested. 3. effective byte programming time 6s, effective word programming time 12s. 4. maximum value measured at worst case conditions for both temperature and v dd after 100,000 program/erase cycles. 5. maximum value measured at worst case conditions for both temperature and v dd . parameters M30LW128D unit min typ (1,2) max (2) block (1mb) erase 1.2 4.8 (4) s chip program (write to buffer) 98 290 (4) s chip erase time 148 440 (4) s program write buffer 192 (3) 576 (4) s word/byte program time (word/byte program command) 16 48 (4) s program suspend latency time 1 20 (5) s erase suspend latency time 1 25 (5) s block protect time 18 30 (5) s blocks unprotect time 0.75 1.2 (5) s program/erase cycles (per block) 100,000 cycles data retention 20 years
25/57 M30LW128D status register the status register provides information on the current or previous program, erase, block protect or blocks unprotect operation. the various bits in the status register convey information and errors on the operation. they are output on dq7-dq0. to read the status register the read status reg- ister command can be issued. the status register is automatically read after program, erase, block protect, blocks unprotect and program/erase re- sume commands. as the device contains two sta- tus registers (one for each internal memory) the status register must be read at the same address as the previous operation. the contents of the status register can be updat- ed during an erase or program operation by tog- gling the output enable pin or by dis-activating and then reactivating the device (refer to table 3). status register bits 5, 4, 3 and 1 are associated with various error conditions and can only be reset with the clear status register command. the sta- tus register bits are summarized in table 11, sta- tus register bits. refer to table 11 in conjunction with the following text descriptions. program/erase controller status (bit 7). the pro- gram/erase controller status bit indicates whether the program/erase controller is active or inactive. when the program/erase controller status bit is low, v ol , the program/erase controller is active and all other status register bits are high imped- ance; when the bit is high, v oh , the program/ erase controller is inactive. the program/erase controller status is low im- mediately after a program/erase suspend com- mand is issued until the program/erase controller pauses. after the program/erase controller paus- es the bit is high. during program, erase, block protect and blocks unprotect operations the program/erase control- ler status bit can be polled to find the end of the operation. the other bits in the status register should not be tested until the program/erase con- troller completes the operation and the bit is high. after the program/erase controller completes its operation the erase status, program status and block protection status bits should be tested for errors. erase suspend status (bit 6). the erase sus- pend status bit indicates that an erase operation has been suspended and is waiting to be re- sumed. the erase suspend status should only be considered valid when the program/erase con- troller status bit is high (program/erase controller inactive); after a program/erase suspend com- mand is issued the memory may still complete the operation rather than entering the suspend mode. when the erase suspend status bit is low, v ol , the program/erase controller is active or has com- pleted its operation; when the bit is high, v oh , a program/erase suspend command has been is- sued and the memory is waiting for a program/ erase resume command. when a program/erase resume command is is- sued the erase suspend status bit returns low. erase status (bit 5). the erase status bit can be used to identify if the device has failed to verify that the block has erased correctly or that all blocks have been unprotected successfully. the erase status bit should be read once the program/erase controller status bit is high (program/erase con- troller inactive). when the erase status bit is low, v ol , the device has successfully verified that the block has erased correctly or all blocks have been unprotected suc- cessfully. when the erase status bit is high, v oh , the erase operation has failed. depending on the cause of the failure other status register bits may also be set to high, v oh . n if only the erase status bit (bit 5) is set high, v oh , then the program/erase controller has applied the maximum number of pulses to the block and still failed to verify that the block has erased correctly or that all the blocks have been unprotected successfully. n if the failure is due to an erase or blocks unprotect with v pen low, v ol , then v pen status bit (bit 3) is also set high, v oh . n if the failure is due to an erase on a protected block then block protection status bit (bit 1) is also set high, v oh . n if the failure is due to a program or erase incorrect command sequence then program status bit (bit 4) is also set high, v oh . once set high, the erase status bit can only be re- set low by a clear status register command or a hardware reset. if set high it should be reset be- fore a new program or erase command is issued, otherwise the new command will appear to fail. program status (bit 4). the program status bit is used to identify a program or block protect fail- ure. the program status bit should be read once the program/erase controller status bit is high (program/erase controller inactive). when the program status bit is low, v ol , the de- vice has successfully verified that the write buffer has programmed correctly or the block is protect- ed. when the program status bit is high, v oh , the program or block protect operation has failed. de- pending on the cause of the failure other status register bits may also be set to high, v oh .
M30LW128D 26/57 n if only the program status bit (bit 4) is set high, v oh , then the program/erase controller has applied the maximum number of pulses to the byte and still failed to verify that the write buffer has programmed correctly or that the block is protected. n if the failure is due to a program or block protect with v pen low, v ol , then v pen status bit (bit 3) is also set high, v oh . n if the failure is due to a program on a protected block then block protection status bit (bit 1) is also set high, v oh . n if the failure is due to a program or erase incorrect command sequence then erase status bit (bit 5) is also set high, v oh . once set high, the program status bit can only be reset low by a clear status register command or a hardware reset. if set high it should be reset be- fore a new program or erase command is issued, otherwise the new command will appear to fail. v pen status (bit 3). the v pen status bit can be used to identify if a program, erase, block protec- tion or block unprotection operation has been at- tempted when v pen is low, v il . when the v pen status bit is low, v ol , no pro- gram, erase, block protection or block unprotec- tion operations have been attempted with v pen low, v il , since the last clear status register com- mand, or hardware reset. when the v pen status bit is high, v oh , a program, erase, block protec- tion or block unprotection operation has been at- tempted with v pen low, v il . once set high, the v pen status bit can only be re- set by a clear status register command or a hard- ware reset. if set high it should be reset before a new program, erase, block protection or block unprotection command is issued, otherwise the new command will appear to fail. program suspend status (bit 2). the program suspend status bit indicates that a program oper- ation has been suspended and is waiting to be re- sumed. the program suspend status should only be considered valid when the program/erase controller status bit is high (program/erase con- troller inactive); after a program/erase suspend command is issued the device may still complete the operation rather than entering the suspend mode. when the program suspend status bit is low, v ol , the program/erase controller is active or has completed its operation; when the bit is high, v oh , a program/erase suspend command has been is- sued and the device is waiting for a program/ erase resume command. when a program/erase resume command is is- sued the program suspend status bit returns low. block protection status (bit 1). the block pro- tection status bit can be used to identify if a pro- gram or erase operation has tried to modify the contents of a protected block. when the block protection status bit is low, v ol , no program or erase operations have been at- tempted to protected blocks since the last clear status register command or hardware reset; when the block protection status bit is high, v oh , a program (program status bit 4 set high) or erase (erase status bit 5 set high) operation has been attempted on a protected block. once set high, the block protection status bit can only be reset low by a clear status register com- mand or a hardware reset. if set high it should be reset before a new program or erase command is issued, otherwise the new command will appear to fail. reserved (bit 0). bit 0 of the status register is reserved. its value should be masked.
27/57 M30LW128D table 11. status register bits operation bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 result (hex) program/erase controller active 0 hi-z n/a write buffer not ready 0 hi-z n/a write buffer ready 1 0 0000080h write buffer ready in erase suspend 1 1 00000c0h program suspended 1 0 0001084h program suspended in erase suspend 1 1 00010c4h program/block protect completed successfully 100000080h program completed successfully in erase suspend 1100000c0h program/block protect failure due to incorrect command sequence 1011000b0h program failure due to incorrect command sequence in erase suspend 1111000f0h program/block protect failure due to v pen error 100110098h program failure due to v pen error in erase suspend 1101100d8h program failure due to block protection 1 0 0100192h program failure due to block protection in erase suspend 1101001d2h program/block protect failure due to cell failure 100100090h program failure due to cell failure in erase suspend 1101000d0h erase suspended 1 1 00000c0h erase/blocks unprotect completed successfully 100000080h erase/blocks unprotect failure due to incorrect command sequence 1011000b0h erase/blocks unprotect failure due to v pen error 1010100a8h erase failure due to block protection 1 0 10001a2h erase/blocks unprotect failure due to failed cells in block 1010000a0h configure sts error due to invalid configuration code 1011000b0h
M30LW128D 28/57 maximum rating stressing the device above the ratings listed in ta- ble 12, absolute maximum ratings, may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicat- ed in the operating sections of this specification is not implied. exposure to absolute maximum rat- ing conditions for extended periods may affect de- vice reliability. refer also to the stmicroelectronics sure program and other rel- evant quality documents. table 12. absolute maximum ratings note: 1. maximum one output short-circuited at a time and for no longer than 1 second. symbol parameter value unit min max t bias temperature under bias C40 125 c t stg storage temperature C55 150 c v io input or output voltage C0.6 v ddq +0.6 v v dd , v ddq supply voltage C0.6 5.0 v i osc output short-circuit current 100 (1) ma
29/57 M30LW128D dc and ac parameters this section summarizes the operating and mea- surement conditions, and the dc and ac charac- teristics of the device. the parameters in the dc and ac characteristics tables that follow, are de- rived from tests performed under the measure- ment conditions summarized in table 13, operating and ac measurement conditions. de- signers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. table 13. operating and ac measurement conditions figure 9. ac measurement input output waveform figure 10. ac measurement load circuit table 14. capacitance note: 1. t a = 25c, f = 1 mhz 2. sampled only, not 100% tested. parameter M30LW128D units min max supply voltage (v dd ) 2.7 3.6 v input/output supply voltage (v ddq ) 2.7 3.6 v ambient temperature (t a ) grade 1 0 70 c grade 6 C40 85 c load capacitance (c l ) 30 pf input pulses voltages 0 to v ddq v input and output timing ref. voltages 0.5 v ddq v ai00610 v ddq 0v 0.5 v ddq ai03459 1.3v dq s c l c l includes jig capacitance 3.3k w 1n914 device under test 0.1f v dd v ddq 0.1f symbol parameter test condition typ max unit c in input capacitance v in = 0v 68pf c out output capacitance v out = 0v 812pf
M30LW128D 30/57 table 15. dc characteristics symbol parameter test condition min max unit i li input leakage current 0v v in v ddq 1 a i lo output leakage current 0v v out v ddq 5 a i dd supply current (random read) e = v il , f=5mhz 20 ma i ddo supply current (page read) e = v il , f=33mhz 29 ma i dd1 supply current (standby) e = v ih , rp = v ih 80 m a i dd5 supply current (auto low-power) e = v il , rp = v ih 80 m a i dd2 supply current (reset/power-down) rp = v il 80 a i dd3 supply current (program or erase, block protect, block unprotect) program or erase operation in progress 30 ma i dd4 supply current (erase/program suspend) e = v ih 80 a v il input low voltage C0.5 0.3v ddq v v ih input high voltage 0.7v ddq v ddq + 0.5 v v ol output low voltage i ol = 100a 0.2 v v oh output high voltage i oh = C100a v ddq C0.2 v v lko v dd supply voltage (erase and program lockout) 2v v penh v pen supply voltage (block erase, program and block protect) 2.7 3.6 v
31/57 M30LW128D figure 11. bus read ac waveforms note: 1. refer to table 3 for details of how the device is enabled. 2. byte can be low or high. the byte signal is not available with the lfbga88 package. table 16. bus read ac characteristics symbol parameter test condition M30LW128D unit 110 t avav address valid to address valid e = v il , g = v il min 110 ns t av qv address valid to output valid e = v il , g = v il max 110 ns t axqx address transition to output transition e = v il , g = v il min 0 ns t blqv byte low (or high) to output valid e = v il , g = v il max 1 s t blqz byte low (or high) to output hi-z e = v il , g = v il max 1 s t ehqx chip enable high to output transition g = v il min 0 ns t ehqz chip enable high to output hi-z g = v il max 25 ns t elbl chip enable low to byte low (or high) g = v il max 10 ns t elqx chip enable low to output transition g = v il min 0 ns t elqv chip enable low to output valid g = v il max 110 ns t ghqx output enable high to output transition e = v il min 0 ns t ghqz output enable high to output hi-z e = v il max 15 ns t glqx output enable low to output transition e = v il min 0 ns t glqv output enable low to output valid e = v il max 25 ns ai07509 e (1) g a0-a23 dq0-dq15 valid taxqx telqx tavqv tglqv tehqz tghqx output tavav tehqx tghqz tglqx telqv byte (2) telbl tblqv tblqz
M30LW128D 32/57 figure 12. page read ac waveforms note: 1. refer to table 3 for details of how the device is enabled. table 17. page read ac characteristics note: for other timings see table 16, bus read ac characteristics. symbol parameter test condition M30LW128D unit 110 t axqx1 address transition to output transition e = v il , g = v il min 6 ns t avqv1 address valid to output valid e = v il , g = v il max 25 ns ai07510 e (1) g a3-a23 dq0-dq15 valid taxqx telqx tavqv tglqv tehqx tghqz output output a1-a2 taxqx1 valid valid tghqx tehqz telqv tglqx tavqv1
33/57 M30LW128D figure 13. write ac waveform, write enable controlled note: 1. refer to table 3 for details of how the device is enabled. 2. not available with the lfbga88 package. table 18. write ac characteristics, write enable controlled symbol parameter test condition M30LW128D unit 110 t av wh address valid to write enable high e = v il min 50 ns t dvwh data input valid to write enable high e = v il min 50 ns t elwl chip enable low to write enable low min 0 ns t vphwh program/erase enable high to write enable high min 0 ns t whax write enable high to address transition e = v il min 0 ns t whbl write enable high to status/(ready/busy) low max 500 ns t whdx write enable high to input transition e = v il min 0 ns t wheh write enable high to chip enable high min 0 ns t ghwl output enable high to write enable low min 20 ns t whgl write enable high to output enable low min 35 ns t whwl write enable high to write enable low min 30 ns t wlwh write enable low to write enable high e = v il min 70 ns ai07511 dq0-dq15 sts (2) (ready/busy mode) w a0-a23 e (1) g input valid twheh tavwh twlwh telwl v pen twhax twhwl twhdx tdvwh tvphwh twhgl tghwl twhbl
M30LW128D 34/57 figure 14. write ac waveforms, chip enable controlled note: 1. refer to table 3 for details of how the device is enabled. 2. not available with the lfbga88 package. table 19. write ac characteristics, chip enable controlled. symbol parameter test condition M30LW128D unit 110 t av eh address valid to chip enable high w = v il min 50 ns t dveh data input valid to chip enable high w = v il min 50 ns t wlel write enable low to chip enable low min 0 ns t vpheh program/erase enable high to chip enable high min 0 ns t ehax chip enable high to address transition w = v il min 5 ns t ehbl chip enable high to status/(ready/busy) low max 500 ns t ehdx chip enable high to input transition w = v il min 5 ns t ehwh chip enable high to write enable high min 0 ns t ghel output enable high to chip enable low min 20 ns t ehgl chip enable high to output enable low min 35 ns t ehel chip enable high to chip enable low min 30 ns t eleh chip enable low to chip enable high w = v il min 70 ns ai07512 dq0-dq15 sts (2) e (1) a0-a23 w g input valid tehwh taveh teleh twlel v pen tehax tehel tehdx tdveh tvpheh tehgl tghel tehbl (ready/busy mode)
35/57 M30LW128D figure 15. reset, power-down and power-up ac waveform note: 1. refer to table 3 for details of how the device is enabled. 2. not available with the lfbga88 package. table 20. reset, power-down and power-up ac characteristics symbol parameter M30LW128D unit 110 t phqv reset/power-down high to data valid max 150 ns t phwl reset/power-down high to write enable low max 1 s t plph reset/power-down low to reset/power-down high min 100 ns t plbh reset/power-down low to status/(ready/busy) high max 30 s t vdhph supply voltages high to reset/power-down high min 0 s ai07513b sts (2) w rp e (1) , g v dd , v ddq tvdhph tplph tplbh power-up and reset reset during program or erase dq0-dq15 tphqv (ready/busy mode) tphwl
M30LW128D 36/57 package mechanical figure 16. tsop56 - 56 lead plastic thin small outline, 14 x 20 mm, package outline note: drawing is not to scale. table 21. tsop56 - 56 lead plastic thin small outline, 14 x 20 mm, package mechanical data symbol mm inches typ min max typ min max a 1.20 0.0472 a1 0.05 0.15 0.0020 0.0059 a2 0.95 1.05 0.0374 0.0413 b 0.17 0.27 0.0067 0.0106 c 0.10 0.21 0.0039 0.0083 d 19.80 20.20 0.7795 0.7953 d1 18.30 18.50 0.7205 0.7283 e 13.90 14.10 0.5472 0.5551 e 0.50 C C 0.0197 C C l 0.50 0.70 0.0197 0.0276 a 0 5 0 5 n56 56 cp 0.10 0.0039 tsop-a d1 e 1 n cp b e a2 a n/2 d die c l a1 a
37/57 M30LW128D figure 17. tbga64 - 10x13mm, 8 x 8 ball array 1mm pitch, package outline note: drawing is not to scale. table 22. tbga64 - 10x13mm, 8 x 8 ball array, 1 mm pitch, package mechanical data symbol millimeters inches typ min max typ min max a 1.200 0.0472 a1 0.300 0.200 0.350 0.0118 0.0079 0.0138 a2 0.850 0.0335 b 0.400 0.500 0.0157 0.0197 d 10.000 9.900 10.100 0.3937 0.3898 0.3976 d1 7.000 C C 0.2756 C C ddd 0.100 0.0039 e 1.000 C C 0.0394 C C e 13.000 12.900 13.100 0.5118 0.5079 0.5157 e1 7.000 C C 0.2756 C C fd 1.500 C C 0.0591 C C fe 3.000 C C 0.1181 C C sd 0.500 C C 0.0197 C C se 0.500 C C 0.0197 C C e1 e d1 d eb sd se a2 a1 a bga-z23 ddd fd fe ball "a1"
M30LW128D 38/57 figure 18. lfbga88 8x10 mm - 8x10 ball array, 0.8mm pitch, bottom view package outline note: drawing is not to scale. table 23. lfbga88 8x10mm - 8x10 ball array, 0.8mm pitch, package mechanical data note: all of the values in the table are preliminary and are subject to change. symbol millimeters inches typ min max typ min max a 1.400 0.0551 a1 0.300 0.0118 a2 0.960 0.0378 b 0.400 0.350 0.450 0.0157 0.0138 0.0177 d 8.000 7.900 8.100 0.3150 0.3110 0.3189 d1 5.600 C C 0.2205 C C ddd 0.100 0.0039 e 10.000 9.900 10.100 0.3937 0.3898 0.3976 e1 7.200 C C 0.2835 C C e2 8.800 C C 0.3465 C C e 0.800 C C 0.0315 C C fd 1.200 C C 0.0472 C C fe 1.400 C C 0.0551 C C fe1 0.600 C C 0.0236 C C sd 0.400 C C 0.0157 C C se 0.400 C C 0.0157 C C a2 a1 a bga-z42 ddd d e e b se fd fe1 e2 d1 sd ball "a1" e1 fe
39/57 M30LW128D part numbering table 24. ordering information scheme note: devices are shipped from the factory with the memory content bits erased to 1. for a list of available options (speed, package, etc...) or for further information on any aspect of this de- vice, please contact the st sales office nearest to you. example: M30LW128D 110 n 1 t device type m30 = multiple memory product, multiple flash architecture l = page mode operating voltage w = v dd = 2.7v to 3.6v, v ddq = 1.8v to v dd device function 128d = two 64 mbit (x8, x16), uniform block speed 110 = 110 ns package n = tsop56: 14 x 20 mm za = tbga64: 10 x 13 mm, 1mm pitch ze = lfbga88 8x10mm - 8x10 active ball array, 0.8mm pitch temperature range 1 = 0 to 70 c 6 = C40 to 85 c option t = tape & reel packing
M30LW128D 40/57 appendix a. block address table table 25. block addresses block no. address range (x8 bus width) address range (x16 bus width) upper memory 128 fe0000h-ffffffh 7f0000h-7fffffh 127 fc0000h-fdffffh 7e0000h-7effffh 126 fa0000h-fbffffh 7d0000h-7dffffh 125 f80000h-f9ffffh 7c0000h-7cffffh 124 f60000h-f7ffffh 7b0000h-7bffffh 123 f40000h-f5ffffh 7a0000h-7affffh 122 f20000h-f3ffffh 790000h-79ffffh 121 f00000h-f1ffffh 780000h-78ffffh 120 ee0000h-efffffh 770000h-77ffffh 119 ec0000h-edffffh 760000h-76ffffh 118 ea0000h-ebffffh 750000h-75ffffh 117 e80000h-e9ffffh 740000h-74ffffh 116 e60000h-e7ffffh 730000h-73ffffh 115 e40000h-e5ffffh 720000h-72ffffh 114 e20000h-e3ffffh 710000h-71ffffh 113 e00000h-e1ffffh 700000h-70ffffh 112 de0000h-dfffffh 6f0000h-6fffffh 111 dc0000h-ddffffh 6e0000h-6effffh 110 da0000h-dbffffh 6d0000h-6dffffh 109 d80000h-d9ffffh 6c0000h-6cffffh 108 d60000h-d7ffffh 6b0000h-6bffffh 107 d40000h-d5ffffh 6a0000h-6affffh 106 d20000h-d3ffffh 690000h-69ffffh 105 d00000h-d1ffffh 680000h-68ffffh 104 ce0000h-cfffffh 670000h-67ffffh 103 cc0000h-cdffffh 660000h-66ffffh 102 ca0000h-cbffffh 650000h-65ffffh 101 c80000h-c9ffffh 640000h-64ffffh 100 c60000h-c7ffffh 630000h-63ffffh 99 c40000h-c5ffffh 620000h-62ffffh 98 c20000h-c3ffffh 610000h-61ffffh 97 c00000h-c1ffffh 600000h-60ffffh 96 be0000h-bfffffh 5f0000h-5fffffh upper memory 95 bc0000h-bdffffh 5e0000h-5effffh 94 ba0000h-bbffffh 5d0000h-5dffffh 93 b80000h-b9ffffh 5c0000h-5cffffh 92 b60000h-b7ffffh 5b0000h-5bffffh 91 b40000h-b5ffffh 5a0000h-5affffh 90 b20000h-b3ffffh 590000h-59ffffh 89 b00000h-b1ffffh 580000h-58ffffh 88 ae0000h-afffffh 570000h-57ffffh 87 ac0000h-adffffh 560000h-56ffffh 86 aa0000h-abffffh 550000h-55ffffh 85 a80000h-a9ffffh 540000h-54ffffh 84 a60000h-a7ffffh 530000h-53ffffh 83 a40000h-a5ffffh 520000h-52ffffh 82 a20000h-a3ffffh 510000h-51ffffh 81 a00000h-a1ffffh 500000h-50ffffh 80 9e0000h-9fffffh 4f0000h-4fffffh 79 9c0000h-9dffffh 4e0000h-4effffh 78 9a0000h-9bffffh 4d0000h-4dffffh 77 980000h-99ffffh 4c0000h-4cffffh 76 960000h-97ffffh 4b0000h-4bffffh 75 940000h-95ffffh 4a0000h-4affffh 74 920000h-93ffffh 490000h-49ffffh 73 900000h-91ffffh 480000h-48ffffh 72 8e0000h-8fffffh 470000h-47ffffh 71 8c0000h-8dffffh 460000h-46ffffh 70 8a0000h-8bffffh 450000h-45ffffh 69 880000h-89ffffh 440000h-44ffffh 68 860000h-87ffffh 430000h-43ffffh 67 840000h-85ffffh 420000h-42ffffh 66 820000h-83ffffh 410000h-41ffffh 65 800000h-81ffffh 400000h-40ffffh block no. address range (x8 bus width) address range (x16 bus width)
41/57 M30LW128D lower memory 64 7e0000h-7fffffh 3f0000h-3fffffh 63 7c0000h-7dffffh 3e0000h-3effffh 62 7a0000h-7bffffh 3d0000h-3dffffh 61 780000h-79ffffh 3c0000h-3cffffh 60 760000h-77ffffh 3b0000h-3bffffh 59 740000h-75ffffh 3a0000h-3affffh 58 720000h-73ffffh 390000h-39ffffh 57 700000h-71ffffh 380000h-38ffffh 56 6e0000h-6fffffh 370000h-37ffffh 55 6c0000h-6dffffh 360000h-36ffffh 54 6a0000h-6bffffh 350000h-35ffffh 53 680000h-69ffffh 340000h-34ffffh 52 660000h-67ffffh 330000h-33ffffh 51 640000h-65ffffh 320000h-32ffffh 50 620000h-63ffffh 310000h-31ffffh 49 600000h-61ffffh 300000h-30ffffh 48 5e0000h-5fffffh 2f0000h-2fffffh 47 5c0000h-5dffffh 2e0000h-2effffh 46 5a0000h-5bffffh 2d0000h-2dffffh 45 580000h-59ffffh 2c0000h-2cffffh 44 560000h-57ffffh 2b0000h-2bffffh 43 540000h-55ffffh 2a0000h-2affffh 42 520000h-53ffffh 290000h-29ffffh 41 500000h-51ffffh 280000h-28ffffh 40 4e0000h-4fffffh 270000h-27ffffh 39 4c0000h-4dffffh 260000h-26ffffh 38 4a0000h-4bffffh 250000h-25ffffh 37 480000h-49ffffh 240000h-24ffffh 36 460000h-47ffffh 230000h-23ffffh 35 440000h-45ffffh 220000h-22ffffh 34 420000h-43ffffh 210000h-21ffffh 33 400000h-41ffffh 200000h-20ffffh 32 3e0000h-3fffffh 1f0000h-1fffffh 31 3c0000h-3dffffh 1e0000h-1effffh 30 3a0000h-3bffffh 1d0000h-1dffffh block no. address range (x8 bus width) address range (x16 bus width) lower memory 29 380000h-39ffffh 1c0000h-1cffffh 28 360000h-37ffffh 1b0000h-1bffffh 27 340000h-35ffffh 1a0000h-1affffh 26 320000h-33ffffh 190000h-19ffffh 25 300000h-31ffffh 180000h-18ffffh 24 2e0000h-2fffffh 170000h-17ffffh 23 2c0000h-2dffffh 160000h-16ffffh 22 2a0000h-2bffffh 150000h-15ffffh 21 280000h-29ffffh 140000h-14ffffh 20 260000h-27ffffh 130000h-13ffffh 19 240000h-25ffffh 120000h-12ffffh 18 220000h-23ffffh 110000h-11ffffh 17 200000h-21ffffh 100000h-10ffffh 16 1e0000h-1fffffh 0f0000h-0fffffh 15 1c0000h-1dffffh 0e0000h-0effffh 14 1a0000h-1bffffh 0d0000h-0dffffh 13 180000h-19ffffh 0c0000h-0cffffh 12 160000h-17ffffh 0b0000h-0bffffh 11 140000h-15ffffh 0a0000h-0affffh 10 120000h-13ffffh 090000h-09ffffh 9 100000h-11ffffh 080000h-08ffffh 8 0e0000h-0fffffh 070000h-07ffffh 7 0c0000h-0dffffh 060000h-06ffffh 6 0a0000h-0bffffh 050000h-05ffffh 5 080000h-09ffffh 040000h-04ffffh 4 060000h-07ffffh 030000h-03ffffh 3 040000h-05ffffh 020000h-02ffffh 2 020000h-03ffffh 010000h-01ffffh 1 000000h-01ffffh 000000h-00ffffh block no. address range (x8 bus width) address range (x16 bus width)
M30LW128D 42/57 appendix b. common flash interface - cfi the common flash interface is a jedec ap- proved, standardized data structure that can be read from the flash memory device. it allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the mem- ory. the system can interface easily with the de- vice, enabling the software to upgrade itself when necessary. when the cfi query command (rcfi) is issued the device enters cfi query mode and the data structure is read from the memory. tables 26, 27, 28, 29, 30 and 31 show the addresses used to re- trieve the data. table 26. query structure overview note: 1. offset 15h defines p which points to the primary algorithm extended query address table. 2. offset 19h defines a which points to the alternate algorithm extended query address table. 3. sba is the start base address for each block. 4. in x8 mode a0 must be set to v il . otherwise, 00h will be output. table 27. cfi - query address and data output note: 1. query data are always presented on dq7-dq0. dq15-dq8 are set to '0'. 2. offset 19h defines a which points to the alternate algorithm extended query address table. 3. in x8 mode a0 must be set to v il . otherwise, 00h will be output. address sub-section name description x16 x8 (4) 0000h 10h manufacturer code 0001h 11h device code 0010h 20h cfi query identification string command set id and algorithm data offset 001bh 36h system interface information device timing and voltage information 0027h 4eh device geometry definition flash memory layout p(h) (1) primary algorithm-specific extended query table additional information specific to the primary algorithm (optional) a(h) (2) alternate algorithm-specific extended query table additional information specific to the alternate algorithm (optional) (sba+02)h block status register block-related information address data description x16 x8 (3) 0010h 20h 51h "q" 51h; "q" query ascii string 52h; "r" 59h; "y" 0011h 22h 52h "r" 0012h 24h 59h "y" 0013h 26h 01h primary vendor: command set and control interface id code 0014h 28h 00h 0015h 2ah 31h primary algorithm extended query address table: p(h) 0016h 2ch 00h 0017h 2eh 00h alternate vendor: command set and control interface id code 0018h 30h 00h 0019h 32h 00h alternate algorithm extended query address table 001ah (2) 34h 00h
43/57 M30LW128D table 28. cfi - device voltage and timing specification note: 1. bits are coded in binary code decimal, bit7 to bit4 are scaled in volts and bit3 to bit0 in mv. 2. bit7 to bit4 are coded in hexadecimal and scaled in volts while bit3 to bit0 are in binary code decimal and scaled in 100mv. 3. not supported. 4. in x8 mode a0 must be set to v il . otherwise, 00h will be output. address data description x16 x8 (4) 001bh 36h 27h (1) v dd min, 2.7v 001ch 38h 36h (1) v dd max, 3.6v 001dh 3ah 00h (2) v pp m in C not available 001eh 3ch 00h (2) v pp max C not available 001fh 3eh 04h 2 n s typical time-out for word, dword prog C not available 0020h 40h 08h 2 n s, typical time-out for max buffer write 0021h 42h 0ah 2 n ms, typical time-out for erase block 0022h 44h 00h (3) 2 n ms, typical time-out for chip erase C not available 0023h 46h 04h 2 n x typical for word dword time-out max C not available 0024h 48h 04h 2 n x typical for buffer write time-out max 0025h 4ah 04h 2 n x typical for individual block erase time-out maximum 0026h 4ch 00h (3) 2 n x typical for chip erase max time-out C not available
M30LW128D 44/57 table 29. device geometry definition note: 1. in x8 mode a0 must be set to v il . otherwise, 00h will be output. 2. n/a = not applicable. only the x16 mode is available with the lfbga88 package. table 30. block status register note: 1. ba specifies the block address location, a22-a17. 2. not supported. address data description x16 x8 (1) 0027h 4eh 18h n where 2 n is number of bytes memory size 0028h 50h 02h device interface 02h is the interface for M30LW128D devices delivered in tsop56 and tbga64 packages (x8 and x16 modes available) n/a (2) 01h 01h is the interface for M30LW128D devices delivered in lfbga88 packages (x16 mode available) 0029h 52h 00h 002ah 54h 05h maximum number of bytes in write buffer, 2 n 002bh 56h 00h 002ch 58h 01h bit7-0 = number of erase block regions in device 002dh 5ah 7fh number (n-1) of erase blocks of identical size; n=128 002eh 5ch 00h 002fh 5eh 00h erase block region information x 256 bytes per erase block (128k bytes) 0030h 60h 02h address data selected block information (ba+2)h (1) bit0 0 block unprotected 1 block protected bit1 0 last erase operation ended successfully (2) 1 last erase operation not ended successfully (2) bit7-2 0 reserved for future features
45/57 M30LW128D table 31. extended query information note: 1. bit7 to bit4 are coded in hexadecimal and scaled in volt while bit3 to bit0 are in binary code decimal and scaled in mv. 2. in x8 mode, a0 must be set to v il , otherwise 00h will be output. address data (hex) description offset x16 x8 (2) (p)h 0031h 62h 50h "p" query ascii string - extended table (p+1)h 0032h 64h 52h "r" (p+2)h 0033h 66h 49h "i" (p+3)h 0034h 68h 31h major version number (p+4)h 0035h 6ah 31h minor version number (p+5)h 0036h 6ch ceh optional feature: (1=yes, 0=no) bit0, chip erase supported (0=no) bit1, suspend erase supported (1=yes) bit2, suspend program supported (1=yes) bit3, protect/unprotect supported (1=yes) bit4, queue erase supported (0=no) bit5, instant individual block locking (0=no) bit6, protection bits supported (1=yes) bit7, page read supported (1=yes) bit8, synchronous read supported (0=no) bit9, multi chip device (1=yes) bit10, simultaneous operations supported (1=yes) bits 11 to 31 reserved for future use (p+6)h 0037h 6eh 06h (p+7)h 0038h 70h 00h (p+8)h 0039h 72h 00h (p+9)h 003ah 74h 01h function allowed after suspend: program allowed after erase suspend (1=yes) bits 1 to 7 reserved for future use (p+a)h 003bh 76h 01h block status register bit0, block protect-bit status active (1=yes) bit1, block lock-down bit status (not available) bits 2 to 15 reserved for future use (p+b)h 003ch 78h 00h (p+c)h 003dh 7ah 33h v dd optimum program/erase voltage conditions (p+d)h 003eh 7ch 00h v pp optimum program/erase voltage conditions (p+e)h 003fh 7eh 01h otp protection: no. of protection register fields (p+f)h 0040h 80h 80h protection registers start address, least significant bits (p+10)h 0041h 82h 00h protection registers start address, most significant bits (p+11)h 0042h 84h 03h n where 2 n is number of factory reprogrammed bytes (p+12)h 0043h 86h 03h n where 2 n is number of user programmable bytes (p+13)h 0044h 88h 03h page read: 2 n bytes (n = bits 0-7) (p+14)h 0045h 8ah 00h synchronous mode configuration fields (p+15)h 0046h 8ch reserved for future use
M30LW128D 46/57 appendix c. flow charts figure 19. write to buffer and program flowchart and pseudo code write to buffer e8h command, block address ai07519 start read status register (1) no b7 = 1 write buffer data, start address yes x = n yes no end no write to buffer timeout write n (2) , block address yes x = 0 write next buffer data, next program address (3) x = x + 1 program buffer to flash confirm d0h read status register (1) no b7 = 1 yes full status register check (4) try again later note 2: n+1 is number of words to be programmed note 3: next program address must have same a5-a21. note 4: a full status register check must be done to check the program operation's success. note 1: status register must be read at the same address as the write to buffer command.
47/57 M30LW128D figure 20. program suspend & resume flowchart and pseudo code note: 1. pa = program address. the program/ erase suspend command must be issued to the same address as the current program com- mand. 2. the read status register command must be issued to the same address as the program/ erase suspend command. 3. pa = program address. the program/ erase resume command must be issued to the same address as the program/ erase sus- pend command. ai07514 read status register (2) yes no b7 = 1 yes no b2 = 1 program continues write ffh program/erase suspend command: C write b0h to address pa do: C read status register while b7 = 1 if b2 = 0, program completed read memory array instruction: C write ffh C one or more data reads from other blocks write d0h add pa (3) program erase resume command: C write d0h to address pa to resume erasure C if the program operation completed then this is not necessary. the device returns to read array as normal (as if the program/erase suspend command was not issued). read data from another block start write b0h add pa (1) program complete write ffh read data
M30LW128D 48/57 figure 21. erase flowchart and pseudo code note: 1. the read status register command must be issued to the same address as the block erase command. 2. if an error is found, the status register must be cleared (clear status register command) before further program or erase ope r- ations. write 20h to block address ai07515 start write d0h to block address read status register (1) yes no b7 = 1 yes no b3 = 0 no b4, b5 = 0 v pen invalid error (2) command sequence error erase command: C write 20h to block address C write d0h to block address (a12-a17) (memory enters read status register after the erase command) do: C read status register C if program/erase suspend command given execute suspend erase loop while b7 = 1 if b3 = 1, v pen invalid error: C error handler if b4, b5 = 1, command sequence error: C error handler yes no b5 = 0 erase error (2) yes no suspend suspend loop if b5 = 1, erase error: C error handler yes end yes no b1 = 0 erase to protected block error if b1 = 1, erase to protected block error: C error handler
49/57 M30LW128D figure 22. erase suspend & resume flowchart and pseudo code note: 1. the program/ erase suspend command must be issued to the same address as the current erase command. 2. the read status register command must be issued to the same address as the program/ erase suspend command. 3. the program/ erase resume command must be issued to the same address as the program/ erase suspend command. ai07516 read status register (2) yes no b7 = 1 yes no b6 = 1 erase continues write ffh program/erase suspend command: C write b0h to ba do: C read status register while b7 = 1 if b6 = 0, erase completed read memory array command: C write ffh C one or more data reads from other blocks write d0h add ba (3) read data from another block or program start write b0h add ba (1) erase complete write ffh read data program/erase resume command: C write d0h to ba to resume the erase operation C if the program operation completed then this is not necessary. the device returns to read mode as normal (as if the program/erase suspend was not issued).
M30LW128D 50/57 figure 23. block protect flowchart and pseudo code note: 1. the read status register command must be issued to the same address as the block protect command. write 01h block address ai07517b yes no b7 = 1 start write 60h block address write ffh read status register (1) block protect sucessful b3 = 1 b4, b5 = 1,1 b4 = 1 v pen invalid error invalid command sequence error block protect error yes yes yes no no no block protect command C write 60h, block adress C write 01h, block adress do: C read status register while b7 = 1 if b3 = 1, v pen invalid error read memory array command: C write ffh if b4 = 1, b5 = 1 invalid command sequence error if b4 = 1, block protect error
51/57 M30LW128D figure 24. blocks unprotect flowchart and pseudo code ai07518b yes no b7 = 1 start write ffh read status register blocks unprotect sucessful b3 = 1 b4, b5 = 1,1 b5 = 1 v pen invalid error invalid command sequence error blocks unprotect error yes yes yes no no no do: C read status register while b7 = 1 if b3 = 1, v pen invalid error read memory array command: C write ffh if b4 = 1, b5 = 1 invalid command sequence error if b5 = 1, blocks unprotect error write d0h write 60h C write 60h C write d0h set a23 low (add 000000h) set a23 high (add 400000h) a23 = low? yes no blocks unprotect command C set address 000000h (a23 low) if a23 = low, C set address 000000h (a23 low) C repeat command
M30LW128D 52/57 figure 25. protection register program flowchart and pseudo code note: 1. pr = protection register 2. the read status register command must be issued to the same address as the protection register program command. write pr add, pr data (1) ai06159b yes no b7 = 1 start write c0h write ffh read status register (2) pr program sucessful b4 = 1 v pen invalid error protection register program error protection register lock error yes yes yes no no no protection register program command C write c0h C write protection register address, protection register data do: C read status register while b7 = 1 read memory array command: C write ffh if b4 = 1 protection register program error b3 = 1 if b3 = 1 v pen invalid error b1 = 1 if b1 = 1 protection register lock error
53/57 M30LW128D figure 26. command interface and program erase controller flowchart (a) note: the commands must be issued to the addresses detailed in the command interface section, table 5. ai03618 read signature yes no 90h read status yes 70h no clear status yes 50h no program buffer load yes e8h no erase set-up yes 20h (1) no erase command error yes ffh wait for command write read array yes d0h no a b no c cfi query yes 98h no d0h yes no program command error note 1. the erase command (20h) can only be issued if the flash is not already in erase suspend.
M30LW128D 54/57 figure 27. command interface and program erase controller flowchart (b) note: the commands must be issued to the addresses detailed in the command interface section, table 5. read status yes no 70h b erase yes ready ? no a b0h no read status yes ready ? no erase suspend yes d0h read array yes erase suspended read status (read status) yes (erase resume) no read status 90h no read signature yes 98h no cfi query yes e8h no program buffer load yes c ai03619 program/erase controller status bit in the status register read status d0h yes no no program command error wait for command write ffh yes read array no
55/57 M30LW128D figure 28. command interface and program erase controller flowchart (c). note: the commands must be issued to the addresses detailed in the command interface section, table 5. read status yes no 70h b program yes ready ? no c b0h no read status yes ready ? no program suspend yes d0h read array yes program suspended read status (read status) yes no (program resume) no read status 90h no read signature yes 98h no cfi query yes ai00618 program/erase controller status bit in the status register read status read array yes no ffh wait for command write
M30LW128D 56/57 revision history table 32. document revision history date version revision details 10-oct-2002 1.0 first issue 11-feb-2003 2.0 device code changed, lfbga88 package added, program /erase times and program/erase endurance cycles table modified, read electronic signature table modified, cfi tables clarified in particular table 31 and 29 (extended query information and device geometry definition). i osc parameter added to absolute maximum ratings table. i dd and v lko clarified and i ddo and v penh parameters added to dc characteristics table. t phwl parameter added to reset, power-down and power-up ac waveforms figure and characteristics table. i dd1 , i dd5 , i dd2 , i dd4 , v il , v ih and v lko values refined in dc characteristics table. chip enable state corrected for power-down in table 4, bus operations. addresses modified for blocks unprotect and configure sts commands in table 5, commands. addresses modified in figure 24, blocks unprotect flowchart and pseudo code. figure 23, block protect flowchart and pseudo code, clarified. blocks temporary unprotect feature of reset/power down pin no longer available. program/erase suspend, write to buffer and program, and block erase commands clarified.
57/57 M30LW128D information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners ? 2003 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malt a - morocco - singapore - spain - sweden - switzerland - united kingdom - united states www.st.com

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